Power MOS devices, including laterally diffused metal-oxide-semiconductor (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. In a conventional LDMOS device, hot-carrier injection (HCI) effects, current crowding in a lightly-doped drain (LDD) region and/or electric field distribution are some of the phenomena which are known to undesirably affect the performance and reliability of the device.
HCI in an MOS device generally results from heating and subsequent injection of carriers into the gate oxide of the device, which results in a localized and nonuniform buildup of interface states and oxide charges near and underneath a gate of the device. As is well known in the art, the buildup of interface states, which are typically defined as trapped charges in an interface between an upper surface of the silicon substrate and an oxide layer formed on the substrate, generally results from a high electric field distribution proximate the silicon/oxide interface. This phenomenon can produce variations in certain characteristics of the MOS device, including threshold voltage, transconductance, drain current, etc., thus undesirably affecting the performance and reliability of the device. It is well known that HCI is a strong function of the internal electric field distributions at the silicon/oxide interface of the MOS device.
In order to reduce HCI effects somewhat in an LDMOS device, it is known that the source metal, which provides electrical connection to the source region of the device, may be extended over the gate so as to form a shielding structure. The source contact may thus be used to form a Faraday shield over the gate, which helps reduce the high electric field concentration near the corners of the gate. However, while the Faraday shield may provide a limited reduction in HCI effects, it typically does not reduce current crowding and confinement in the LDD region of the device. It is this current crowding and confinement, particularly near an edge of the gate and in the thin LDD region near a silicon/oxide interface in the device, which primarily contributes to HCI.
As an added drawback, the conventional shielding structure prevents full gate metallization, which is one known method for dramatically reducing the resistance Rg of the gate, thus limiting the high-frequency performance of the LDMOS device. Since the output gain of the MOS device is inversely proportional to the gate resistance of the device, increasing the gate resistance results in a decrease in the output gain of the device, which is particularly undesirable in an amplifier application.
There exists a need, therefore, for an MOS device capable of improved performance and reliability that does not suffer from at least the above-noted deficiencies typically affecting conventional MOS devices. Furthermore, it would be desirable if such an MOS device was fully compatible with a CMOS process technology.